1. Technical Field
This present disclosure relates to circuitry and methods for clock generation. More particularly, the present disclosure relates to fully digital circuits and methods for generating sub clock divisions and clock waves with low skew and simplified implementation.
2. Background Art
Clock generation is very important to efficient low power designs. Most clock generation systems are built in a manner which introduces skew, using complicated selection mechanisms or a cascade of flip flops which generate low order divided clocks. Several pertinent clock generation prior art documents are listed below.
U.S. Pat. No. 5,552,732—“High speed divide by 1.5 clock generator” uses a divide by 3 circuit with 3 gates.
US Patent Application US2011/0234265—“Programmable frequency divider” demonstrates a divide by programmable integer factors.
U.S. Pat. No. 4,866,741—“3/2 frequency divider” employs two D-type flip-flops, an OR gate and an AND gate.
U.S. Pat. No. 7,801,263—“Clock divider with a rational division factor” (Haimzon) provides methods, apparatus, and systems for dividing an input clock or master clock by an integer or non-integer divisor and generating one or more balanced, e.g., 50% duty cycle, divided that are phase-aligned to the input clock.
U.S. Pat. No. 7,667,517—“System and method for fully digital clock divider with non-integer divisor support” provides a system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer.